View GS4576S18GL-24IT_3898506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary gs4576s09/18l 64m x 9, 32m x 18 576mb sio low latency dram (lldram tm ) ii 533 mhz ? 300 mhz 2.5 v v ext 1.8 v v dd 1.5 v or 1.8 v v ddq 144-ball bga commercial temp industrial temp rev: 1.01 4/2011 1/64 ? 2011, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? pin- and function-compatible with micron rldram? ii ? 533 mhz ddr operation (1.067gb/s/pin data rate) ? 38.4 gb/s peak bandwidth (x18 at 533 mhz clock frequency) ? 32m x 18 and 64m x 9 organizations available ? 8 banks ? reduced cycle time (15 ns at 533 mhz) ? address multiplexing (nonmultiplexed address option available) ? sram-type interface ? programmable read latency (r l), row cycle time, and burst sequence length ? balanced read and write latencies in order to optimize data bus uti lization ? data mask for write commands ? differential input clocks (ck, ck ) ? differential input data clocks (dkx, dkx ) ? on-chip dll generates ck edge-aligned data and output data clo ck signals ? data valid signal (qvld) ? 32 ms refresh (16k refresh for each bank; 128k refresh command must be issued in total each 32 ms) ? 144-ball bga package ? hstl i/o (1.5 v or 1.8 v nominal) ? 25 ?6 0 matched impedance outputs ? 2.5 v v ext , 1.8 v v dd , 1.5 v or 1.8 v v ddq i/o ? on-die termination (odt) r tt ? commerical and industrial temperature commercial (+0 t c +95c) industrial (?40 t c +95c) introduction the gsi technology 576mb low latency dram (lldram?) ii is a high speed memory device designed for high address rate data processing typically found in networking and telecommunications appli cations. the 8-bank architecture and low trc allows access rates formerly only found in srams. the double data rate (ddr) i/o interface provides high bandwidth data transfers, clocking out two beats of data per clock cycle at the i/o balls. source-synchronous clocking can be implemented on the host de vice with the provided free- running data output clock. commands, addresses, and control signals are single data rate sign als clocked in by the true differential input clock transition, while input data is clocked in on both crossings of the input data clock(s). read and write data transfers al ways i n short bursts. the burst length is programmable to 2, 4 or 8 by setting the mode register. the device is supplied with 2.5 v v ext and 1.8 v v dd for the core, and 1.5 v or 1.8 v for the hstl output drivers. internally generated row addr esses faci litate bank-scheduled refresh. the device is delivered in an efficent bga 144-ball package.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 2/64 ? 2011, gsi technology 64m x 9 mb ball a ssignments?144-ball bga?top view 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd dnu 3 dnu 3 v ssq v ssq q0 d0 v dd c v tt dnu 3 dnu 3 v ddq v ddq q1 d1 v tt d a22 1 dnu 3 dnu 3 v ssq v ssq qk0 qk0 v ss e a21 dnu 3 dnu 3 v ddq v ddq q2 d2 a20 f a5 dnu 3 dnu 3 v ssq v ssq q3 d3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h ba2 a9 v ss v ss v ss v ss a4 a3 j nf 2 nf 2 v dd v dd v dd v dd ba0 ck k dk dk v dd v dd v dd v dd ba1 ck l ref cs v ss v ss v ss v ss a14 a13 m we a16 a17 v dd v dd a12 a11 a10 n a18 dnu 3 dnu 3 v ssq v ssq q4 d4 a19 p a15 dnu 3 dnu 3 v ddq v ddq q5 d5 dm r v ss dnu 3 dnu 3 v ssq v ssq q6 d6 v ss t v tt dnu 3 dnu 3 v ddq v ddq q7 d7 v tt u v dd dnu 3 dnu 3 v ssq v ssq q8 d8 v dd v v ref zq v ext v ss v ss v ext tdo tdi notes: 1. reserved for future use. this pin may be connected to ground. 2. no function. this pin may have par asitic characteristics of a clock input signal. it may be connected to gnd. 3. do not use. this pin may have parasitic c haracteristics of an i/o. it may be connecte d to gnd.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 3/64 ? 2011, gsi technology 32m x 18 ball assignments?144-ball bga?top view 1 2 3 4 5 6 7 8 9 10 11 12 a v ref v ss v ext v ss v ss v ext tms tck b v dd d4 q4 v ssq v ssq q0 d0 v dd c v tt d5 q5 v ddq v ddq q1 d1 v tt d a22 1 d6 q6 v ssq v ssq qk0 qk0 v ss e a21 2 d7 q7 v ddq v ddq q2 d2 a20 f a5 d8 q8 v ssq v ssq q3 d3 qvld g a8 a6 a7 v dd v dd a2 a1 a0 h ba2 a9 v ss v ss v ss v ss a4 a3 j nf 3 nf 3 v dd v dd v dd v dd ba0 ck k dk dk v dd v dd v dd v dd ba1 ck l ref cs v ss v ss v ss v ss a14 a13 m we a16 a17 v dd v dd a12 a11 a10 n a18 d14 q14 v ssq v ssq q9 d9 a19 p a15 d15 q15 v ddq v ddq q10 d10 dm r v ss qk1 qk1 v ssq v ssq q11 d11 v ss t v tt d16 q16 v ddq v ddq q12 d12 v tt u v dd d17 q17 v ssq v ssq q13 d13 v dd v v ref zq v ext v ss v ss v ext tdo tdi notes: 1. reserved for future use. this pin may be connected to gnd. 2. reserved for future use. this pin may have parasitic characteristics of an address input sign al. it may be connected to gnd. 3. no function. this pin may have par asitic characteristics of a clock i nput signal. it may be connected to gnd.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 4/64 ? 2011, gsi technology ball descriptions symbol type description a0?a21 input address inputs ?a0?a21 define the row and column addresses for read and write operations. during a mode register set (mrs), the address inputs define the register settings. they are sampled at the rising edge of ck. ba0?b2 input bank address inputs ?select to which internal bank a command is being applied. ck, ck input input clock ?ck and ck are differential input clocks. a ddresses and commands are latched on the rising edge of ck. ck is ideally 180o out of phase with ck. cs input chip select ? cs enables the command decoder when low and disables it when high. when the command decoder is disabled, new commands are ignored, but internal operations continue. d0?d17 input data input ?the d signals form the 18-bit input data bus. during write commands, the data is sampled at both edges of dk. dk, dk input input data clock ?dk and dk are the differential input data clocks . all input data is referenced to both edges of dk. dk is ideally 180o out of phase with dk. in both the x9 and x18 devices, all ds are referenced to dk and dk . dm input input data mask ?the dm signal is the input mask signal for write data. input data is masked when dm is sampled high. dm is sampled on both edges of dk. tie signal to ground if not used. tck input ieee 1149.1 clock input ?this ball must be tied to v ss if the jtag function is not used. tms, tdi input ieee 1149.1 test inputs ?these balls may be left as no connects if the jtag function is not used. we , ref input command inputs ?sampled at the positive edge of ck, we and ref define (together with cs ) the command to be executed. v ref input input reference voltage ?nominally v ddq /2. provides a reference voltage for the input buffers. zq i/o external impedance (25?60 ) ?this signal is used to tune the dev ice outputs to the system data bus impedance. q output impedance is set to 0.2 * rq, where rq is a resistor from this signal to ground. connecting zq to gnd invokes the mini mum impedance mode. connecting zq to v dd invokes the maximum impedance mode. refer to the mode register definition diagrams (mode register bit 8 (m8)) to activate or deactivate this function. q0?q17 output data output ?the q signals form the 18-bit output da ta bus. during read commands, the data is referenced to both edges of qk. qk x, qk x output output data clocks ?qkx and qk x are opposite polarity, output data clocks. they are free running, and during reads, are edge-aligned with data output from the lldram ii. qk x is ideally 180o out of phase with qkx. for the x18 device, qk0 and qk0 are aligned with q0?q8, while qk1 and qk1 are aligned with q9?q17. for the x9 devic e, all qs are aligned with qk0 and qk0 . qvld output data valid ?the qvld pin indicates valid output data. qvld is edge-aligned with qkx and qk x.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 5/64 ? 2011, gsi technology tdo output ieee 1149.1 test output ?jtag output. this ball may be left as no connect if the jtag function is not used. v dd supply power supply ?nominally, 1.8 v. see the dc electrical characteristics and operating conditions section for range. v ddq supply dq power supply ?nominally, 1.5 v or 1.8 v. isolated on the device for improved noise immunity. see the dc electrical charac teristics and operating c onditions section for range. v ext supply power supply ?nominally, 2.5 v. see the dc electrical characteristics and operating conditions section for range. v ss supply ground v ssq supply dq ground ?isolated on the device for improved noise immunity. v tt ? power supply ?isolated termination supply. nominally, v ddq /2. see the dc electrical characteristics and operating conditions section for range. a22 ? reserved for future use ?this signal is not connect ed and may be connected to ground. dnu ? do not use ?these balls may be connected to ground. nf ? no function ?these balls can be connected to ground. ball descriptions (continued) symbol type description
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 6/64 ? 2011, gsi technology functional block diagram 2 bank 0 row- address latch and decoder column decoder 16,384 32 i/o gating dqm mask logic 16,384 bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 bank 0 bank 0 memory array (16,384 x 32 x 16 x 9) 2 sense amplifiers read logic q latch qk/qk generator drivers dll ck/ck rcvrs write fifo and drivers clk in input logic dk/dk qk0/qk0 qvld zq cal dm d0?d8 command decode odt control zq cal (0...8) v tt r tt output drivers address register ck a0?a21 1 ba0?ba2 odt control mode register zq 3 1 9 9 9 2 9 9 9 control logic bank control logic column- address counter/ latch row- address mux refresh counter 3 8 1 3 1 8 8 14 5 14 14 n n 25 18 8 1 ck we cs ref odt control v tt r tt 288 288 288 q0?q8 notes: 1. example for bl = 2; column address will be reduced with an increase in burst length. 2. 16 = (length of burst) x 2^(number of column addresses to write fifo and read logic). 3. 64m x 9 drawing shown for reference.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 7/64 ? 2011, gsi technology operations initialization a specific power-up and initialization sequ ence must be observed. other sequences may result in undefined operations or permanent damage to the device. power-up: 1. apply power (v ext , v dd , v ddq , v ref , v tt ) . start clock after the supply voltages are stable. apply v dd and v ext before or at the same time as v ddq 1 . apply v ddq before or at the same time as v ref and v tt . the chip starts internal initlization only after both voltages approach their nominal levels. ck/ ck must meet v id ( dc ) prior to being applied 2 . apply only nop commands to start. ensuring ck/ ck meet v id ( dc ) while loading nop commands guarantees that the lldram ii will not receive damaging comm ands during initialization. 2. idle with continuing nop commands for 200 s (min). 3. issue three or more consecutive mrs commands: two or more dummies plus one valid mrs. the consecutive mrs commands will reset internal logic of the lldram ii. t mrsc does not need to be met between these consecutive commands. address pins should be held low during the dummy mrs commands. 4. t mrsc after the valid mrs, issues an auto refresh comm and to all 8 banks in any order (along with 1024 nop commands) prior to normal operation. as always, t rc must be met between any auto refresh and any subsequent valid command to the same bank. notes: 1. it is possible to apply v ddq before v dd . however, when doing this, the ds, dm, qs and all other pins with an output driver, will go high instead of tri-stating. these pins will remain high until v dd is at the same level as v ddq . care should be taken to avoid bus conflicts during this period. 2. if v id ( dc ) on ck/ ck can not be met prior to being applied to the lldram ii, placing a large external resistor from cs to v dd is a viable option for ensuring the co mmand bus does not receive unwanted co mmands during this unspecified state.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 8/64 ? 2011, gsi technology power?up initialization sequence 200us min mode initialization tmrsc refresh 1024 cycles nop cycles min nop nop mrs mrs mrs nop aref aref nop ac code(1,2) code(1,2) code(2) addr bank 0 bank 7 valid tdkl tdk tdkl tdkhtdkh tdk tck tckl tckh tck v ext v dd v ddq v ref v tt ck ck dk dk command addr ba dm d all banks(5) notes: 1. recommend all address pins held low during dummy mrs commands. 2. a10?a17 must be low. 3. dll must be reset if tck or v dd are changed. 4. ck and ck must be separated at all times to prevent bogus commands from being issued. 5. the sequence of the eight auto refresh commands (with respect to the 1024 nop commands) does not matter. as is required for a ny operation, trc must be met between an auto refresh command and a subsequent valid command to the same bank.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 9/64 ? 2011, gsi technology power?up initialization flow chart v dd and v ext ramp v ddq ramp apply v ref and v tt apply stable ck/ck and dk/dk wait at least 200 s issue mrs command?a10?a17 must be low issue mrs command?a10?a17 must be low desired load mode register with a10?a17 low assert nop for tmrsc issue auto refresh to bank 0 issue auto refresh to bank 1 issue auto refresh to bank 2 issue auto refresh to bank 3 issue auto refresh to bank 4 issue auto refresh to bank 5 issue auto refresh to bank 6 issue auto refresh to bank 7 wait 1024 nop commands * valid command step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 voltage rails can be applied simultaneously mrs commands must be on consecutive clock cycles *note: the sequence of the eight auto refresh comm ands (with respect to the 102 4 nop commands) does not matter. as is required for any operation, trc must be met between an auto refresh command and a subsequent valid command to the same bank.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 10/64 ? 2011, gsi technology dll reset mode register bit 7 (m7) selects dll reset as is shown in th e mode register definition tables. the default setting for m7 is low?dll disabled. once m7 is set high, 1024 cycles (5 s at 200 mhz) are needed before a read command can be issued. the delay allows the internal clock to be synchronized with the ex ternal clock. failing to wait for synchronization to occur may re sult in a violation of the t ckqk parameter. a reset of the dll is necessary if t ck or v dd is changed after the dll has been enabled. to reset the dll, set m7 is low. after waiting t mrsc, an mrs command should be issued to set m7 high. 1024 clock cycles must pass before loading the next read command. driver impedance mapping the lldram ii is equipped with programmable impedance output buffers. setting mode regist er bit 8 (m8) high during the mrs command activates the output impedance control. programmable impedance output buff ers allow the user to match the driver impedance to the pcb trace impedance. to adjust the impedance, an external resistor (rq) is connected between the zq ball and v ss . the value of the resistor must be five times the desired impedance (e.g., a 300 resistor produces an output impedance of 60 ). rq values of 125 ?300 are supported, allowing an output impedance range of 25?60 (+/- 15 %). the drive impedance of uncompensated output transistors can change over time due to changes in supply voltage and die temperature. when drive impedan ce control is enabled in the mrs, the value of rq is periodical ly sampled and needed impedance updates are made automatically. up dates do not affect normal device operation or signal timing. when bit m8 is set low during the mrs command, the output compensation circuits are still active but reference an internal resistance reference. the internal referen ce is imprecise and subject to temperature and voltage variations so output buffers a re set to a nominal output impedance of 50 , but are subject to a 30 percent vari ance over commercial temperature range.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 11/64 ? 2011, gsi technology on?die termination (odt) mode register bit 9 (m9) set to 1 during an mrs command en able s odt. with odt on, the ds, qs, and dm are terminated to v tt with a resistance, r tt . command, address, qvld, and clock signals ar e not terminated. the diagram below shows the equivalent circuit of a d receiver with odt. when a q begins to drive after a read command is i ssued, the odt function is brief ly switched off. when a q stops driving at the end of a data transf er, odt is switched back on. d and dm pins are always terminate d. on?die termination dc parameters description symbol min max units notes termination voltage v tt 0.95 * v ref 1.05 * v ref v 1, 2 on?die termination r tt 125 185 3 notes: 1. all voltages referenced to v ss (gnd). 2. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. the r tt value is measured at 95c t c . v tt sw r tt receiver d v ref on?die termination? equivalent circuit
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 12/64 ? 2011, gsi technology read nop read on-die termination burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 rd nop rd nop nop nop nop nop nop a a ba0 ba2 q0a q0b q2a q2b odt on odt off odt on odt off odt on rl = 4 rc = 4rc = 4 ck ck cmd addr ba qkx qkx qvld q odt
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 13/64 ? 2011, gsi technology read-write on-die termination burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 rd wt nop nop nop nop nop nop nop a a ba0 ba1 d1a d1b q0a q0b odt on odt off odt on rl = 4 wl = 5 ck ck cmd addr ba dk dk dm d qkx qkx q qvld odt
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 14/64 ? 2011, gsi technology read burst on-die termination burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 rd rd rd nop nop nop nop nop nop a a a ba0 ba1 ba2 q0a q0b q1a q1b q2a q2b odt on odt off odt on rl = 4 rc = 4rc = 4 ck ck cmd addr ba qkx qkx qvld q odt
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 15/64 ? 2011, gsi technology commands valid control commands are listed below. any input commands not shown are illegal or reserved. all inputs must meet specified setup and hold times around the true crossing of ck. description of commands command description notes dsel/nop the nop command is used to perform a no operation to the ll dram ii, which essentially deselects the chip. use the nop command to prevent unwanted commands from being registered during idle or wait states. operations already in progress are not affected. output values depend on command history. 1 mrs the mode register is set via the address inputs a0?a17. see the mode register defini tion diagrams for further information. the mrs command can only be issued when all banks are idle and no bursts are in progress. ? read the read command is used to initiate a burst read access to a bank. the value on the ba0?ba2 inputs selects the bank, and the address provided on inputs a0?a n selects the data location within the bank. 2 write the write command is used to initiate a burst write access to a bank. the value on the ba0?ba2 inputs selects the bank, and the address provided on inputs a0?a n selects the data location within the bank. input data appearing on the ds is written to the memo ry array subject to the dm input logic level appearing coincident with the data. if the dm signal is registered low, the corresponding data will be written to memory. if the dm signal is registered high, the corresponding data inputs will be ignored (that is, this part of the data word will not be written). 2 aref the aref command is used during nor ma l operation of the lldram ii to refresh the memory content of a bank. the command is non-persistent, so it must be issued each time a re fresh is required. the value on the ba0?ba2 inputs selects the bank. the re fresh address is generated by an internal refresh controller, effectively making each address bi t a ?don?t care? during the aref command. see the auto refresh section for more details. ? notes: 1. when the chip is deselected, internal nop commands are generated and no commands are accepted. 2. for the value of ?n?, see address widths at different burst lengths table. command table operation command cs we ref a0?a n ba0?ba2 notes device deselect/no operation dsel/nop h x x x x 1 mrs mrs l l l code x 1, 3 read read l h h a ba 1, 2 write write l l h a ba 1, 2 auto refresh aref l h l x ba 1 notes: 1. x= don?t care; h = logic high; l = logic low; a = v alid address; ba = valid bank address. 2. for the value of ?n?, see address widths at different burst lengths table. 3. only a0?a17 are used for the mrs command.
initialization sequence dsel/ nop read write mrs aref notes: automatic sequence command sequence preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 16/64 ? 2011, gsi technology state diagram
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 17/64 ? 2011, gsi technology mode register set mode register set controls the operating modes of the memory, inclu ding configuration, burst length, test mode, and i/o options . during an mrs command, the address inputs a0?a17 are sampled and stored in the mode register. except during initialization to force internal reset, af ter a valid mrs command, t mrsc must be met before any comman d except nop can be issued to the lldram ii. all banks must be idle and no bursts may be in progress when an mrs command is loaded. note: chan ging the burst length configuration ma y scramble previously written data. a bu rst length change must be assumed to invalidate all stored data. mode register set cod ck ck cs we ref a(17:0) a(18:20) ba(2:0)
m2 m1 m0 configuration 000 1 3 (default) 001 1 3 010 2 011 3 100 4 3 101 5 1 1 0 reserved 1 1 1 reserved m4 m3 burst length 0 0 2 (default) 01 4 10 8 11reserved m5 address mux 0 nonmulitplexed (default) 1 multiplexed m7 dll reset 0 dll reset 4 (default) 1 dll enabled m9 on die termination 0 off (default) 1on m8 drive impedance 0 internal 50 5 (default) 1 external (zq) a10 a17 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ... 17?10 9 8 7 6 5 4 3 2 1 0 reserved 1 odt im dll na 2 am bl config address bus mode register (mx) preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 18/64 ? 2011, gsi technology mode register definition in nonmultiplexed address mode notes: 1. a10?a17 must be set to zero; a18?an = ?don?t care?. 2. a6 not used in mrs. 3. bl = 8 is not available. 4. dll reset turns the dll off. 5. +/?30% over rated temperature range.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 19/64 ? 2011, gsi technology configuration tables the relationship between cycle time and read/w rite latency is selected by the user. the configuration table below lists valid configurations available via mode register bits m0, m1, and m2 and the clock fre quencies supported for each setting. write latency is equal to the read latency plus on e in each configuration to reduce bus conflicts . cycle time and read/write latency configuration t able parameter configuration units 1 3 2 3 4 3, 4 5 trc 4 6 8 3 5 tck trl 4 6 8 3 5 tck twl 5 7 9 4 6 tck valid frequency range 266?175 400?175 533?175 200?175 333?175 mhz notes: 1. trc < 20 ns in any configuration is only available with ?18 and ? 24 speed grades. 2. minimum operating frequency for -18 is 370 mhz. 3. bl= 8 is not available. 4. the minimum trc is typically 3 cycles, ex cept in the case of a w rite followed by a read to the same bank. in this instance t he minimum trc is 4 cycles.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 20/64 ? 2011, gsi technology burst length read and write data transfers occur in bursts of 2, 4, or 8 beats. burst length is programmed by the user via mode register bit 3 (m3) and bit 4 (m4). the read burst length diagrams illustrate the different burst lengths with respect to a read command. changes in the burst length affect the width of the address bus. note: chan ging the burst length configuration ma y scramble previously written data. a bu rst length change must be assumed to invalidate all stored data. read burst lengths read q0 q1 read nop nop nop nop nop nop nop q0 q1 q2 q3 read nop nop nop nop nop nop nop q0 q1 q2 q3 q4 q5 q6 q7 rl = 5 rl = 5 rl = 5 example bl=2 example bl=4 example bl=8 ck ck command qkx qkx qvld q ck1 ck1 command1 qkx1 qkx1 qvld1 q1 ck2 ck2 command2 qkx2 qkx2 qvld2 q2 address widths at di fferent burst lengths burst length configuration x 9 x 18 2 a0?a21 a0?a20 4 a0?a20 a0?a19 8 a0?a19 a0?a18
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 21/64 ? 2011, gsi technology write write data transfers are launched with a write c ommand, as shown below. a valid ad dress must be provided during the write command. during write data transfers, each beat of incoming data is regist ered on crossings of dk and dk until the burst transfer is complete. write latency (wl) that is always one cycle longer th an the programmed read latency (rl), so the first valid data registered at the first true cr ossing of the dk clocks wl cycles after the write command. since the input and output buses are separated, any write burst may be follo wed by a subsequent read command without encountering external data bus contentio n. the write-to-read timing diagrams illus trate the timing requirements for a write followed by a read. setup and hold times for incomi ng d relative to the dk edges are specified as t ds and t dh. input data may be masked a high on an associated dm pin. the setup and hold times for the dm signal are t ds and t dh. write command a ba ck ck cs we ref address bank address
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 22/64 ? 2011, gsi technology write burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 wr wr wr wr wr wr wr wr wr a a a a a a a a a ba0 ba1 ba2 ba3 ba0 ba4 ba5 ba6 ba7 d0a d0b d1a d1b d2a d2b d3a d3b wl = 5 rc = 4rc = 4 ck ck cmd addr ba dk dk dm d write burst length 4, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 wr nop wr nop wr nop wr nop wr a a a a a ba0 ba1 ba0 ba3 ba0 d0a d0b d0c d0d d1a d1b d1c d1d wl = 5 rc = 4rc = 4 ck ck cmd addr ba dk dk dm d
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 23/64 ? 2011, gsi technology write-read burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 wr rd rd nop nop nop nop nop nop nop a a a ba0 ba1 ba2 d0a d0b q1a q1b q2a q2b wl = 5 rl = 4 ck ck cmd addr ba dk dk dm d q qvld qkx qkx
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 24/64 ? 2011, gsi technology write-read burst lengt h 4, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 wr rd wr rd nop nop nop nop nop nop a a a a ba0 ba1 ba2 ba3 d0a d0b d0c d0d d2a d2b d2c d2d q1a q1b q1c q1d q3a q3b q3c q3d rl = 4 wl = 5 ck ck cmd addr ba dk dk dm d qkx qkx q qvld
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 25/64 ? 2011, gsi technology read read data transfers are launched with a read command, as show n below. read addresses must provided with the read command. each beat of a read data transf er is edge-aligned with the qk x signals. after a programma ble read latency, data is available at the outputs. one half clock cycle prior to valid data on the read bus , the data valid signal (qvld) is driven high. qvld is also ed ge- aligned with the qk x signals. the qk clocks are free-running. the skew between qk and the crossi ng point of ck is specified as t ckqk. t qkq0 is the skew between qk0 and the last valid data edge generated at the q signals associated with qk0 ( t qkq0 is referenced to q0?q8). t qkq1 is the skew between qk1 and the last valid data edge generated at the q signals associated with qk1 ( t qkq1 is referenced to q9?q17). t qkq x is derived at each qk x clock edge and is not cumulative over time. t qkq is defined as the skew between either qk differenti al pair and any output data edge. at the end of a burst transfer, assuming no other commands have b een initiated, output data (q) will go high-z. the qvld signal transitions low on the beat of a read burst. note that if ck/ ck violates the v id(dc) specification while a read burst is occurring, qvld remains high until a dummy read command is issued. back-to-back read commands are possible, producing a continuous flow of output data. the data valid window specification is referenced to qk transitions and is defined as: t qhp ? ( t qkq [max] + | t qkq [min]|). see the read data valid window section for illustration. any read transfer may be followed by a subsequent write comm and. the read-to-w rite timing diagram illustrates the timing requirements for a read followed by a write. read command a ba ck ck cs we ref address bank address
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 26/64 ? 2011, gsi technology read burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 rd rd rd rd rd rd rd rd rd a a a a a a a a a ba0 ba1 ba2 ba3 ba0 ba7 ba6 ba5 ba4 q0a q0b q1a q1b q2a q2b q3a q3b q0a rl = 4 rc = 4rc = 4 ck ck cmd addr ba qkx qkx qvld q read burst length 4, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 rd nop rd nop rd nop rd nop rd a a a a a ba0 ba1 ba0 ba1 ba3 q0a q0b q0c q0d q1a q1b q1c q1d q0a rl = 4 rc = 4rc = 4 ck ck cmd addr ba qkx qkx qvld q
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 27/64 ? 2011, gsi technology read-write burst length 2, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 wr rd rd nop nop nop nop nop nop nop a a a ba0 ba1 ba2 d0a d0b q1a q1b q2a q2b rl = 4 wl = 5 ck ck cmd addr ba dk dk dm d qkx qkx q qvld
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 28/64 ? 2011, gsi technology read-write burst length 4, configuration 1 t0 t1 t2 t3 t4 t5 t6 t7 rd wr rd nop nop nop nop nop a a a ba0 ba1 ba2 d1a d1b d1c d1d q0a q0b q0c q0d q2a q2b q2c rl = 4 wl = 5 ck ck cmd addr ba dk dk dm d qkx qkx q qvld
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 29/64 ? 2011, gsi technology auto refresh the auto refresh (aref) comma nd launches a refresh cycle on one row in th e bank addressed. refresh row addresses are generated by an internal refresh counter, so address inputs are don?t care, but a bank addresses (ba 2:0) must be provided duri ng the aref command. a refresh may be contining in one ba nk while other commands, including other aref commands, are launched in other banks. the delay between the aref command and a read, write or aref command to the same bank must be at least t rc. the entire memory must be refreshed every 32 ms ( t ref). this means that this 576mb devi ce requires 128k refresh cycles at an average periodic in terval of 0.24 s max (actual periodic refresh interval is 32 ms/16k rows/8 = 0.244 s). to improve efficiency, eight aref commands (one for each bank) can be launched at periodic intervals of 1.95 s (32 ms/16k rows = 1.95 s). the auto refresh cycle diagram illustrates an example of a refresh sequence. auto refresh (aref) command ba ck ck cs we ref address bank address auto refresh cycle aref aref nop aref ba0 ba3 ba4 ck ck cmd bank
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 30/64 ? 2011, gsi technology address multiplexing lldram ii defaults to ?broadside? addressi ng at power up, meaning, it registers all ad dress inputs on a single clock transition . however, for most configurations of the device, considerable ef ficiency can be gained by operating in address multiplexed mode, cutting the address pin count on the host device in half. in multiplexed address mode, the address is loaded in two consecutive clock transitions. broadside addressing only improves continuous burs t mode data transfer efficiency of burst length 2 (bl = 2) configuration. in address multiplex mode, bank addresses are loaded on the same clock transition as command and th e first half of the address , a x . the 576mb address mapping in multiplexed address mode table and cycle time and read/write latency configuration in mulitplexed mode table show the addresses needed for both the first and s econd clock transitions (a x and a y , respectively). the aref command does not require an address on the second clock tr ansition, as only the bank a ddress are loaded for refresh commands. therefore, aref commands ma y be issued on consecutive clocks, even when in address multiplex mode. setting mode register bit 5 (m5) to 1 in the mode register activates the multiplexed addr ess mode. once this bit is set subsequent mrs, read, and write operate as desc ribed in the multiplexed address mode diagram.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 31/64 ? 2011, gsi technology power-up multiplexed address mode 200us min tmrsc tmrsc refresh 1024 nop cycles min nop nop mrs mrs mrs nop mrs nop rf0 rf7 nop ac code(1,2) code(1,2) code(2,3) ax(2,4) ay(2) valid(5) bank 0 bank 7 valid(5) tdkl tdk tdkl tdkhtdkh tdk tckl tck tckl tckhtckh tck v ext v dd v ddq v ref v tt ck ck dk dk command addr bank all banks(9) notes: 1. recommended that all address pins held low during dummy mrs commands. 2. a10?a18 must be low. 3. set address a5 high. this enbles the part to enter multiplexed address mode when in non-multiplexed mode operation. multiplex ed address mode can also be entered at some later time by issuing an mrs command with a5 high. once address bit a5 is set high, tm rsc must be satisfied before the two-cycle multiplexed mode mrs command is issued. 4. address a5 must be set high. this and the following step set the desired mode register once the lldram ii is in multiplexed a ddress mode. 5. any command or address. 6. the above sequence must be followed in order to power up the lldram ii in the multiplexed address mode. 7. dll must be reset if tck or v dd are changed. 8. ck and ck must separated at all times to pr event bogus commands from being issued. 9. the sequence of the eight auto refresh co mmands (with respect to the 1024 nop commands) does not matter. as is required for a ny operation, trc must be met between an auto refresh command and a subsequent valid command to the same bank.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 32/64 ? 2011, gsi technology mrs command in multiplexed mode the mode register set command stores the data for controlling the ram into the mode register. the register allows the user to modify read and write pipeline length, burst length, test mode, and i/o options. the multiplexed mrs command requires two cycles to complete the ax address is sampled on the true cr ossing of clock with the mrs command. the ay address and a required nop command are captured on the next next cro ssing of clock. after issuing a valid mrs command, t mrsc must be met before any read, write, mrs, or aref command can be issu ed to the lldram ii. this stat ement does not apply to the consecutive mrs commands needed for intern al logic reset during the initialization rout ine. the mrs command can only be issued when all banks are idle an d no bursts are in progress. note: the data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed. mrs command in multiplexed mode mrs ax ay ck ck cs we ref a(9:0) a(18:10) ba(2:0)
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 33/64 ? 2011, gsi technology mode register definition in multiplexed address mode m2 m1 m0 configuration 000 1 2 (default) 001 1 2 010 2 011 3 100 4 2 101 5 1 1 0 reserved 1 1 1 reserved m4 m3 burst length 0 0 2 (default) 01 4 10 8 11reserved m5 address mux 0 nonmulitplexed (default) 1 multiplexed m7 dll reset 0 dll reset 4 (default) 1 dll enabled m9 on die termination 0 off (default) 1on m8 drive impedance 0 internal 50 3 (default) 1 external (zq) a18...a10 a9 a8 a4 a3 18?10 9 8 7 6 5 4 3 2 1 0 reserved 1 odt im dll na 5 am bl config mode register (mx) a18...a10 a9 a8 a5 a4 a3 a0 a y a x notes: 1. a10?a18 must be set to zero. 2. bl = 8 is not available. 3. +/?30% over rated temperature range. 4. dll reset turns the dll off. 5. ay8 not used in mrs. 6. ba0?ba2 are ?don?t care?. 7. addresses a0, a3, a4, a5, a8, and a9 must be set as shown in order to activate the mode register in the multiplexed address m ode.
576mb address mapping in mu ltiplexed address mode data width burst length ball address a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 x18 2 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 4 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 8 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 x a11 a12 a16 a15 x9 2 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay a20 a1 a2 a21 a6 a7 a19 a11 a12 a16 a15 4 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay a20 a1 a2 x a6 a7 a19 a11 a12 a16 a15 8 ax a0 a3 a4 a5 a8 a9 a10 a13 a14 a17 a18 ay x a1 a2 x a6 a7 a19 a11 a12 a16 a15 notes: x= don?t care. preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 34/64 ? 2011, gsi technology configuration in mulitplexed mode in multiplexed address mode, th e read and write latencies are increased by on e clock cycle. however, the lldram ii cycle time remains the same as when in nonmultiplexed address mode. cycle time and read/write latency configuration in mulitplexed mode parameter configuration units 1 3 2 3 4 3, 4 5 trc 4 6 8 3 5 tck trl 5 7 9 4 6 tck twl 6 8 10 5 7 tck valid frequency range 266?175 400?175 533?175 200?175 333?175 mhz notes: 1. trc < 20 ns in any configuration is only available with ?24 and ? 18 speed grades. 2. minimum operating frequency for ?18 is 370 mhz. 3. bl = 8 is not available. 4. the minimum trc is typically 3 cycles, ex cept in the case of a write followed by a read to the same bank. in this instance th e minimum trc is 4 cycles.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 35/64 ? 2011, gsi technology write command in multiplexed mode address multiplexed write data tr ans fers are launched with a write command, as shown below. a valid address must be provided during the write command. th e ax address must be loaded on the same true cl ock crossing used to lo ad the write command and the bank address. the ay address and a nop comman d must be provided at the next clock crossing. during write data transfers, each beat of incoming data is regi stered on crossings of dk and dk until the burst transfer is complete. write latency (wl) is always one cycl e longer than the programmed read latency (rl). a write burst may be followed by a read command (assuming t rc is met). the write-to-read timing diagrams illustrate the timing requirements for a write followed by a read. setup and hold times for incoming d relative to the dk edges are specified as t ds and t dh. input data may be masked high on an associated dm pin. the setup and hold ti mes for the dm signal are t ds and t dh. write command in multiplexed mode write ax ay ba ck ck cs we ref address bank address write burst length 4, configur ation 1 in multiplexed mode t0 t1 t2 t3 t4 t5 t6 t7 t8 wr nop wr nop wr nop wr nop wr ax ay ax ay ax ay ax ay ax ba0 ba1 ba0 ba3 ba0 d0a d0b d0c d0d d1a d1b wl = 6 rc = 4rc = 4 ck ck cmd addr ba dk dk dm d
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 36/64 ? 2011, gsi technology read command in multiplexed mode address multiplexed read data tr ansfers are launched with a read command, as s hown below. a valid address must be provided during the read command. the a x address must be loaded on the same true clock crossing used to load the read command and the bank address. the a y address and a nop command must be provided at the next clock crossing. each beat of a read data transf er is edge-alig ned with the qkx signals. after a programmable read latency, data is available at the outputs. one half clock cycle prior to valid data on the r ead bus, the data valid signal (qvl d) is driven high. qvld is als o edge-aligned with the qkx signals. the qk clocks are free-running. the skew between qk and the crossi ng point of ck is specified as t ckqk. t qkq0 is the skew between qk0 and the last valid data edge generated at the q signals associated with qk0 ( t qkq0 is referenced to q0?q8). t qkq1 is the skew between qk1 and the last valid data edge generated at the q signals associated with qk1 ( t qkq1 is referenced to q9?q17). t qkq x is derived at each qk x clock edge and is not cumulative over time. t qkq is defined as the skew between either qk differenti al pair and any output data edge. at the end of a burst transfer, assuming no oth er commands have been initiated, output data (q) will go high?z. the qvld signal transitions low on the beat of a read burst. note that if ck/ ck violates the v id(dc) specification while a read burst is occurring, qvld remains high until a dummy read command is issued. back-to-back read commands are possible, producing a continuous flow of output data. the data valid window specification is referenced to qk transitions and is defined as: t qhp ? ( t qkq [max] + | t qkq [min]|). see the read data valid window section. any read transfer may be followed by a subsequent write comm and. the read-to-w rite timing diagram illustrates the timing requirements for a read followed by a write. read command in mulitplexed mode read ax ay ba ck ck cs we ref address bank address
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 37/64 ? 2011, gsi technology read burst length 4, confi guration 1 in multiplexed mode t0 t1 t2 t3 t4 t5 t6 t7 t8 rd nop rd nop rd nop rd nop rd ax ay ax ay ax ay ax ay ax ba0 ba1 ba2 ba0 ba1 q0a q0b q0c q0d q1a q1b q1c rl = 5 ck ck cmd addr ba qkx qkx q qvld
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 38/64 ? 2011, gsi technology refresh commands in multiplexed address mode the aref command launches a refresh cycle on one row in the bank addressed. refresh row addresses are generated by an internal refresh counter. so address inputs are don?t care, but bank addresses (ba 2:0) must be provided during the aref command. a refresh may be continuing in one bank while other commands, including other aref commands, are launched in other banks. the delay between the aref command and a read, write or aref command to the same bank must be at least t rc. the entire memory must be refreshed every 32 ms ( t ref). this means that this 576mb device requires 128k refresh cycles at an average periodic in terval of 0.24 s max (actual periodic refresh interval is 32 ms/16k rows/8 = 0.244 s). to improve efficiency, eight aref commands (one for each bank) can be launched at periodic intervals of 1.95 s (32 ms/16k rows = 1.95 s). the auto refresh cycle diagram illustrates an example of a refresh sequence. unlike read and write commands in address multiplex mode, all the informa tion needed to ex ecute an aref command (the aref command and the band address (ba 2:0)) is loaded in a single clock crossing, another aref command (to a different bank) may be loaded on the next clock crossing. consecutive refresh operations with multiplexed mode t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ac 1 nop aref aref aref aref aref aref aref aref ac 1 nop ax ay ax ay ban ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 ban ck ck cmd addr ba notes: 1. any command. 2. bank n is chosen so that t rc is met.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 39/64 ? 2011, gsi technology absolute maximum ratings absolute maximum voltage (all voltages reference to v ss ) parameter min max unit i/o voltage ?0.3 v ddq + 0.3 v voltage on v ext supply ?0.3 +2.8 v voltage on v dd supply relative to v ss ?0.3 +2.1 v voltage on v ddq supply relative to v ss ?0.3 +2.1 v note: permanent damage to the device may occur if the absolute maximum ratings are exceede d. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. absolute maximum temperature parameter temperature ran ge symbol min. max. unit notes storage temperature ? t stg ?55 +150 c 1 reliability junc tion temperature commercial t j ? +110 c 2 industrial ? +110 c 2 notes: 1. max storage case temperature; t stg is measured in the center of the package. 2. temperatures greater than 110 c may cause permanent damage to the device. this is a stress rating only and f unctional operation of the device at or above this is not implied. exposure to the absolute maximum ratings c ondtions for extended periods may affect rel iability of the part.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 40/64 ? 2011, gsi technology recommended operating temper ature and thermal impedance like any other semiconcuctor device, the lldram ii must be operated within the temperatur e specifications shown in the temperature limits table for the device to meet datasheet specifications. the therma l impedance characteristics of the device a re are listed below. in applications where th e ambient temperature or pcb temperature ar e too high, use of forced air and/or heat sinks may be required in order to sati sfy the case temperat ure specifications. temperature limits parameter temperature r ange symbol min. max. unit notes operating junction temperature commercial t j 0 +100 c 1 industrial ?40 +100 c 1 operating case temperature commercial t c 0 +95 c 2, 3 industrial ?40 +95 c 2, 3, 4 notes: 1. junction temperature depends upon package type, cycle ti me, loading, ambient temperature, and airflow. 2. maximum operating case temperature, t c , is measured in the center of the package. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. junction and case temperature specifications must be satisfied. thermal impedance package test pcb substrate ja (c/w) airflow = 0 m/s ja (c/w) airflow = 1 m/s ja (c/w) airflow = 2 m/s jb (c/w) jc (c/w) bg a 2-layer tbd tbd tbd tbd tbd 4-layer tbd tbd tbd tbd tbd notes: 1. thermal impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number. 2. please refer to jedec standard jesd51-6. 3. the characteristics of the test fixture pcb influence reported the rmal characteristics of the device. the minimal metalizatio n of a 2-layer board tends to minimize the utility of t he junction-to-board heat path. the 4-layer te st fixture pcb is intended to highlight t he effect of connection to power planes typically found in the pcbs used in most applications. be advised that a good thermal path to the pcb can result in cooling or heating of the ram depending on pcb temperature.
recommended dc operat ing conditions and elect rical characteristics description conditions symbol min. max. unit notes supply voltage ? v ext 2.38 2.63 v ? supply voltage ? v dd 1.7 1.9 v 2 isolated output buffer supply ? v ddq 1.4 v dd v 2, 3 reference voltage ? v ref 0.49 * v ddq 0.51 * v ddq v 4, 5, 6 termination voltage ? v tt 0.95 * v ref 1.05 * v ref v 7, 8 input high (logic 1) voltage ? v ih(dc) v ref + 0.1 v ddq + 0.3 v 2 input low (logic 0) voltage ? v il(dc) v ssq ? 0.3 v ref ? 0.1 v 2 ouput high current v out = v ddq /2 i oh (v ddq /2)/(1.15 * rq/5) (v ddq /2)/(0.85 * rq/5) a 9, 10, 11 ouput low current v out = v ddq /2 i ol (v ddq /2)/(1.15 * rq/5) (v ddq /2)/(0.85 * rq/5) a 9, 10, 11 clock input leakage current 0 v v in v dd i lc ?5 5 a ? input leakage current 0 v v in v dd i li ?5 5 a ? output leakage current 0 v v in v ddq i lo ?5 5 a ? reference voltage current ? i ref ?5 5 a ? notes: 1. all voltages referenced to v ss (gnd). this note applies to the entire table. 2. overshoot v ih(ac) v dd + 0.7 v for t tck/2. undershoot: v il(ac) ?0.5 v for t tck/2. during normal operation v ddq must not exceed v dd . control input signals may not have pulse widthts less than tck/2 or operate at frequencies exceeding tck (max). 3. v ddq can be set to a nominal 1.5 v 0.1 v or 1.8 v 0.1 v supply. 4. typically the value of v ref is expected to be 0.5 * v ddq of the transmitting device. v ref is expected to track variations in v ddq . 5. peak-to-peak ac noise on v ref must not exceed 2% of v ref(dc) . 6. v ref is expected to equal v ddq /2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2% of the dc value. thus, from v ddq /2, v ref is allowed 2% v ddq /2 for dc error and an addtional 2% v ddq /2 for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. on-die termination may be selected using mode register bit 9 (m9). a resistance r tt from each data input signal to the nearest v tt can be enabled. r tt = 125 ?185 at 95 c t c . 9. i oh and i ol are defined as absolute val ues and are measured at v ddq /2. i oh flows from the device, i ol flows into the device. 10. if mode register bit 8 (m8) is 0, use rq = 250 in the equation in lieu of presence of an external impedance ma tched resistor. 11. for v ol and v oh , refer to the lldram ii ibis models. preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 41/64 ? 2011, gsi technology
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 42/64 ? 2011, gsi technology dc differential input clock logic levels parameter symbol min. max. unit notes clock input voltage level: ck and ck v in(dc) ?0.3 v ddq + 0.3 v 1?4 clock input differential voltage: ck and ck v id(dc) 0.2 v ddq + 0.6 v 1?5 notes: 1. dkx and dkx have the same requirements as ck and ck . 2. all voltages referenced to v ss (gnd). 3. the ck and ck input reference level (for timing referenced to ck/ ck ) is the point at which ck and ck cross. the input reference level for signals other than ck/ ck is v ref. 4. the ck and ck input slew rate must be 2 v/ns ( 4 v/ns if measured differentially). 5. v id is the magnitude of the difference between the input level on ck and the input level on ck . recommended ac operat ing conditions and elect rical characteristics input ac lo gic levels parameter symbol min. max. unit notes input high (logic 1) voltage v ih v ref + 0.2 ? v 1, 2, 3 input low (logic 0) voltage v il ? v ref ? 0.2 v 1, 2, 3 notes: 1. all voltages referenced to v ss (gnd). 2. the ac and the dc input level specifications are defined in the hstl standard (that is, the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that st ate as long as the signal does not ring back above (see drawing b elow) the dc input low (high) level). 3. the minimum slew rate for the input signals used to te st the device is 2 v/ns in the range between v il(ac) and v ih(ac) . v ih(dc)min v ref v il(dc)max v ddq v ih(ac)min v il(ac)max v ssq v swing(ac) (min) nominal tas/ tcs/ tds and tah/ tch/ tdh slew rate
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 43/64 ? 2011, gsi technology ac differential input clock levels parameter symbol min. max. unit notes clock input differential voltage: ck and ck v id(ac) 0.4 v ddq + 0.6 v 1?5 clock input crossing point voltage: ck and ck v ix(ac) v ddq /2 ? 0.15 v ddq /2 + 0.15 v 1?4, 6 notes: 1. dkx and dkx have the same requirements as ck and ck . 2. all voltages referenced to v ss (gnd). 3. the ck and ck input reference level (for timing referenced to ck/ ck ) is the point at which ck and ck cross. the input reference level for signals other than ck/ ck is v ref. 4. the ck and ck input slew rate must be 2 v/ns ( 4 v/ns if measured differentially). 5. v id is the magnitude of the difference between the input level on ck and the input level on ck . 6. the value of v ix is expected to equal v ddq /2 of the transmitting device and must track va riations in the dc level of the same. v in(dc) max ck ck v ddq /2 + 0.15 v ddq /2 v ddq /2 ? 0.15 v in(dc) min v ix(ac)max v ix(ac)min maximum clock level minimum clock level v id(ac) 3 v id(dc) 2 1 differential clock input requirements notes: 1. ck and ck must cross within this region. 2. ck and ck must meet at least v id(dc)min when static and centered around v ddq /2. 3. minimum peak-to-peak swing. 4. it is a violation to tristate ck and ck after the part is initialized.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 44/64 ? 2011, gsi technology input slew rate derating the address and command setup and hold derating values show n in the following table should be added to the default t as/ t cs/ t ds and t ah/ t ch/ t dh specifications when the slew rate of any of these input signals is less than the 2 v/ns. to determine the setup and hold time n eeded for a given slew rate, add the t as/ t cs default specification to the ? t as/ t cs v ref to ck/ ck crossing? and the t ah/ t ch default specification to the " t ah/ t ch ck/ ck crossing to v ref " derated values in the address and command setup and hold derating values table. the derated da ta setup and hold values can be determined the same way using the ? t ds v ref to ck/ ck crossing? and ? t dh to ck/ ck crossing to v ref ? values in the data setup and hold derating values table. the derating values apply to all speed grades. the setup times in the table relate to a rising signal. the time from the rising signal crossing v ih(ac)min to the ck/ ck cross point is static and must be maintained across all slew rates. the de rated setup timing describes the point at which the rising signal crosses v ref(dc) to the ck/ ck cross point. this derated value is calculated by dete rmining the time needed to maintain the given slew rate and the delta between v ih(ac)min and the ck/ ck cross point. all these same values ar e also valid for falling signals (with respect to v il(ac)max and the ck/ ck cross point). the hold times in the table relate to falling signals. the time from the ck/ ck cross point to when the signal crosses v ih(dc) min is static and must be maintained across all slew rates. the derated hold timing describes the delta between the ck/ ck cross point to when the falling signal crosses v ref(dc) . this derated value is calculated by determining the time needed to maintain the given slew rate and the delta between the ck/ ck cross point and v ih(dc) . the hold values are also valid for rising signals (with respect to v il(dc)max and the ck and ck cross point). note: the above descriptions also pertain to data setup and hold derating when ck/ ck are replaced with dk/ dk .
address and command setup and hold derating values command/address slew rate (v/ns) tas/tcs v ref to ck/ ck crossing tas/tcs v ih(ac)min ck/ ck crossing tah/tch ck/ ck crossing to v ref tah/tch ck/ ck crossing to v ih(dc)min units ck/ ck differential slew rate: 2.0 v/ns 2.0 0 ?100 0 ?50 ps 1.9 5 ?100 3 ?50 ps 1.8 11 ?100 6 ?50 ps 1.7 18 ?100 9 ?50 ps 1.6 25 ?100 13 ?50 ps 1.5 33 ?100 17 ?50 ps 1.4 43 ?100 22 ?50 ps 1.3 54 ?100 27 ?50 ps 1.2 67 ?100 34 ?50 ps 1.1 82 ?100 41 ?50 ps 1.0 100 ?100 50 ?50 ps ck/ ck differential slew rate: 1.5 v/ns 2.0 30 ?70 30 ?20 ps 1.9 35 ?70 33 ?20 ps 1.8 41 ?70 36 ?20 ps 1.7 48 ?70 39 ?20 ps 1.6 55 ?70 43 ?20 ps 1.5 63 ?70 47 ?20 ps 1.4 73 ?70 52 ?20 ps 1.3 84 ?70 57 ?20 ps 1.2 97 ?70 64 ?20 ps 1.1 112 ?70 71 ?20 ps 1.0 130 ?70 80 ?20 ps ck/ ck differential slew rate: 1.0 v/ns 2.0 60 ?40 60 10 ps 1.9 65 ?40 63 10 ps 1.8 71 ?40 66 10 ps 1.7 78 ?40 69 10 ps 1.6 85 ?40 73 10 ps 1.5 93 ?40 77 10 ps 1.4 103 ?40 82 10 ps 1.3 114 ?40 87 10 ps 1.2 127 ?40 94 10 ps 1.1 142 ?40 101 10 ps 1.0 160 ?40 110 10 ps preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 45/64 ? 2011, gsi technology
data setup and hold derating values data slew rate (v/ns) tds v ref to ck/ ck crossing tds v ih(ac)min ck/ ck crossing tds ck/ ck crossing to v ref tds ck/ ck crossing to v ih(dc)min units dk/ dk differential slew rate: 2.0 v/ns 2.0 0 ?100 0 ?50 ps 1.9 5 ?100 3 ?50 ps 1.8 11 ?100 6 ?50 ps 1.7 18 ?100 9 ?50 ps 1.6 25 ?100 13 ?50 ps 1.5 33 ?100 17 ?50 ps 1.4 43 ?100 22 ?50 ps 1.3 54 ?100 27 ?50 ps 1.2 67 ?100 34 ?50 ps 1.1 82 ?100 41 ?50 ps 1.0 100 ?100 50 ?50 ps dk/ dk differential slew rate: 1.5 v/ns 2.0 30 ?70 30 ?20 ps 1.9 35 ?70 33 ?20 ps 1.8 41 ?70 36 ?20 ps 1.7 48 ?70 39 ?20 ps 1.6 55 ?70 43 ?20 ps 1.5 63 ?70 47 ?20 ps 1.4 73 ?70 52 ?20 ps 1.3 84 ?70 57 ?20 ps 1.2 97 ?70 64 ?20 ps 1.1 112 ?70 71 ?20 ps 1.0 130 ?70 80 ?20 ps dk/ dk differential slew rate: 1.0 v/ns 2.0 60 ?40 60 10 ps 1.9 65 ?40 63 10 ps 1.8 71 ?40 66 10 ps 1.7 78 ?40 69 10 ps 1.6 85 ?40 73 10 ps 1.5 93 ?40 77 10 ps 1.4 103 ?40 82 10 ps 1.3 114 ?40 87 10 ps 1.2 127 ?40 94 10 ps 1.1 142 ?40 101 10 ps 1.0 160 ?40 110 10 ps preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 46/64 ? 2011, gsi technology
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 47/64 ? 2011, gsi technology capacitance description symbol conditions min. max. unit address/control input capacitance c i ta = 25 c; f = 100 mhz v dd = v ddq = 1.8 v 1.0 2.0 pf input/output capacitance (d, q, dm, and qk, qk ) c o 3.0 4.5 pf clock capacitance (ck/ ck and dk/ dk ) c ck 1.5 2.5 pf jtag pins c jtag 1.5 4.5 pf notes: 1. capacitance is not tested on the zq pin. 2. jtag pins are tested at 50 mhz. idd operating conditions description condition symbol -18 -24 -25 -33 units standby current tck = idle, all banks idle; no inputs toggling . i sb 1 (v dd ) x9/x18 tbd tbd tbd tbd ma i sb 1 (v ext ) tbd tbd tbd tbd active standby current cs = 1, no commands; bank address incremented and half address/data change once every four clock cycles. i sb 2 (v dd ) x9/x18 tbd tbd tbd tbd ma i sb 2 (v ext ) tbd tbd tbd tbd operational current bl = 2, sequential bank access; bank transitions once every trc; half address transitions once every trc; read followed by w rite sequence; continuous data during write commands. i dd 1 (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 1 (v ext ) tbd tbd tbd tbd operational current bl = 4, sequential bank access; bank transitions once every t rc ; half address transitions once every t rc ; read followed by write sequence; continuous data during write commands. i dd 2 (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 2 (v ext ) tbd tbd tbd tbd operational current bl = 8, sequential bank access; bank transitions once every t rc ; half address transitions once every t rc . read followed by write sequence; continuous data during write commands. i dd 3 (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 3 (v ext ) tbd tbd tbd tbd burst refresh current eight bank cyclic refresh; continuous address/data; command bus remains in refresh f or all eight banks. i ref 1 (v dd ) x9/x18 tbd tbd tbd tbd ma i ref 1 (v ext ) tbd tbd tbd tbd distributed refresh current single bank refresh; sequential bank access; half address transitions once every trc; continuous data. i ref 2 (v dd )x9/x18 tbd tbd tbd tbd ma i ref 2 (v ext ) tbd tbd tbd tbd
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 48/64 ? 2011, gsi technology operating burst write current example bl= 2; cyclic bank access; half of address bits change every clock cycle; continuous data; measurement is taken during continuous write. i dd 2w (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 2w (v ext ) tbd tbd tbd tbd operating burst write current example bl= 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during continuous write. i dd 4w (v dd )x9/x18 tbd tbd tbd tbd ma i dd 4w (v ext ) tbd tbd tbd tbd operating burst write current example bl= 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during continuous write. i dd 8w (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 8w (v ext ) tbd tbd tbd tbd operating burst read current example bl= 2; cyclic bank access; half of address bits change every clock cycle; continuous data; measurement is taken during continuous read. i dd 2r (v dd )x9/x18 tbd tbd tbd tbd ma i dd 2r (v ext ) tbd tbd tbd tbd operating burst read current example bl= 4; cyclic bank access; half of address bits change every two clock cycles; continuous data; measurement is taken during continuous read. i dd 4r (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 4r (v ext ) tbd tbd tbd tbd operating burst read current example bl= 8; cyclic bank access; half of address bits change every four clock cycles; continuous data; measurement is taken during continuous read. i dd 8r (v dd ) x9/x18 tbd tbd tbd tbd ma i dd 8r (v ext ) tbd tbd tbd tbd notes: 1. i dd specifications are tested after the device is properly initiali zed and is operating at worst-case rated temperature and voltage specifications. 2. definitions of idd conditions: 3a. low is defined as v in v il ( ac ) max . 3b. high is defined as v in > v ih ( ac ) min . 3c. stable is defined as inputs remaining at a high or low level. 3d. floating is defined as inputs at v ref = v ddq /2. 3e. continuous data is defined as half the d or q signals changng between high and low every half clock cycle (twice per clock) . 3f. continuous address is defined as half the address signals changing between high and low every clock cycles (once per clock ). 3g. sequential bank access is defined as the bank address incrementing by one every t rc. 3h. cyclic bank access is defined as the bank address incrementing by one for each command access. for bl = 2 this is every clo ck, for bl = 4 this is every other clock, and for bl = 8 this is every fourth clock. 3. cs is high unless a read, write, aref, or mrs command is registered. cs never transitions more than once per clock cycle. 4. i dd parameters are specified with odt disabled. 5. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 6. i dd tests may use a v il -to-v ih swing of up to 1.5 v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ ck ), and parameter specifications are tested for the specified ac input levels under normal use conditions. the minimum slew rate for th e input signals used to test the device is 2 v/ns in the range between v il ( ac ) andv ih ( ac ) . idd operating condi tions (continued) description condition symbol -18 -24 -25 -33 units
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 49/64 ? 2011, gsi technology ac electrical characteristics parameter symbol ?18 ?24 ?25 ?33 units notes min max min max min max min max clock input clock cycle time tck 1.875 2.7 2.5 5.7 2.5 5.7 3.3 5.7 ns ? input data clock cycle time tdk tck tck tck tck ns ? clock jitter: period tjit per ?100 100 ?150 150 ?150 150 ?200 200 ps 5, 6 clock jitter: cycle-to-cycle tjit cc ? 200 ? 300 ? 300 ? 400 ps ? clock high time tckh tdkh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ? clock low time tckl tdkl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck ? clock to input data clock tckdk ?0.3 0.3 ?0.45 0.5 ?0.45 0.5 ?0.45 1.2 ns ? mode register set cycle time to any command tmrsc 6 ? 6 ? 6 ? 6 ? tck ? setup times address/command and input setup time tas/tcs 0.3 ? 0.4 ? 0.4 ? 0.5 ? ns ? data?in and data mask to dk set up time tds 0.17 ? 0.25 ? 0.25 ? 0.3 ? ns ? hold times address/command and input hold time tah/tcs 0.3 ? 0.4 ? 0.4 ? 0.5 ? ns ? data-in and data mask to dk setup time tdh 0.17 ? 0.25 ? 0.25 ? 0.3 ? ns ? data and data strobe output data clock high time tqkh 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ckh ? output data clock low time tqkl 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 t ckl ? half?clock period tqhp min (tqkh, tqkl) ? min (tqkh, tqkl) ? min (tqkh, tqkl) ? min (tqkh, tqkl) ? ? ? qk edge to clock edge skew tckqk ?0.2 0.2 ?0.25 0.25 ?0.25 0.25 ?0.3 0.3 ns ? qk edge to output data edge tqkq0, tqkq1 ?0.12 0.12 ?0.2 0.2 ?0.2 0.2 ?0.25 0.25 ns 7 qk edge to any output data edge tqkq ?0.22 0.22 ?0.3 0.3 ?0.3 0.3 ?0.35 0.35 ns 8 qk edge to qvld tqkvld ?0.22 0.22 ?0.3 0.3 ?0.3 0.3 ?0.35 0.35 ns ? data valid window tdvw tdvw (min) ? tdvw (min) ? tdvw (min) ? tdvw (min) ? ? 9
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 50/64 ? 2011, gsi technology refresh average periodic refresh interval trefi ? 0.24 ? 0.24 ? 0.24 ? 0.24 10 notes: 1. all timing parameters are measured rela tive to the cro ssing point of ck/ ck , dk/ dk and to the crossing point with v ref of the command, address, and data signals. 2. outputs measured with equivalent load: v tt 50 test point 10 pf q 3. tests for ac timing i dd , and electrical ac and dc characteri stics may be conducted at nominal re ference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 4. ac timing may use a v il ? to?v ih swing of up to 1.5 v in the test environmen t, but input timing is still referenced to v ref (or to the crossing point for ck/ ck ), and parameter specifications are tested for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals used to test t he device is 2 v/ns in the rance between v il(ac) and v ih(ac) . 5. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 6. frequency drift is not allowed. 7. tqkq0 is referenced to q0?q8. tqkq1 is referenced to q9?q17. 8. tqkq takes in to account the skew between any qk x and any q. 9. tdvw (min) tqhp ? (tqkqx [ max] + |tqkqx [min]|) 10. to improve efficiency, eight aref co mmands (one for each bank) can be posted to t he lldram ii on consecutive cycles at perio dic intervals of 1.95 s . ac electrical character istics (continued) parameter symbol ?18 ?24 ?25 ?33 units notes min max min max min max min max
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 51/64 ? 2011, gsi technology read data valid wi ndow for x18 device b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" x"zzz" x"155" x"0aa" x"zzz" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" b"1" b"0" b"0" b"1" x"zzz" x"0aa" x"155" x"zzz" tqkq1(min) tdvw3 tqkq0(max) tdvw3 tqkq1(min) tdvw3 tqkq1(max) tdvw3 tqkq1(min) tqhp1tqhp1 tqhp1tqhp1 tqkq0(min)tqkq0(min) tdvw3 tqkq0(max) tdvw3 tqkq0(min)tqkq0(min) tdvw3 tqkq0(max) tdvw3 tqkq0(min)tqkq0(min) tqhp1tqhp1 tqhp1tqhp1 qk0 qk0 q_lower_0 q_lower_1 q_lower_2 q_lower_3 q_lower_4 q_lower_5 q_lower_6 q_lower_7 q_lower_8 q_lower qk1 qk1 q_upper_9 q_upper_10 q_upper_11 q_upper_12 q_upper_13 q_upper_14 q_upper_15 q_upper_16 q_upper_17 q_upper notes: 1. tqhp is defined as the lesser of tqkh or tqkl. 2. tqkq0 is referenced to q0?q8. 3. minimum data valid window (tdvw) c an be expressed as tqhp ? (tqkq x [max] + |tqkq x [min]|). 4. tqkq1 is referenced to q9?q17. 5. tqkq takes into account the skew between any qk x and any q.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 52/64 ? 2011, gsi technology read burst timing q0 q1 q2 q3 tdvwtdvw tqkqmin tqkqmax tqkvld tqkvld tqkhtqkh tqkltqkl tckqk tcktck tckltckl tckhtckh ck ck qkx qkx qvld q ieee 1149.1 serial boundary scan (jtag) lldram ii includes an ieee 1149.1 (jtag) serial boundary s can test access port (tap). jtag ports are generally used to verify the connectivity of the device once it has been mounted on a printed circuit board (pcb). th e port operates in accordanc e with ieee standard 1149.1-2001 (jtag). because the zq pin is actually an analog output , to ensure proper b oundary-scan testing of the zq pin, mode register bit 8 (m8) needs to be set to 0 until the jtag testing of the pin is complete. note that upon pow er up, the default state of mode register bit 8 (m8) is low. whenever the jtag port is used prior to the initialization of th e lldram ii device, such as wh en initial conectivity testing is conducted, it is cri tical that the ck and ck pins meet v id(dc) or that cs be held high from power-up until testing begins. failure to do so can result in inadvertent mrs commands being loaded and causing unexpected test re sults. alternately a partial initialization can be conducted that consists of simply loading a single mrs command with desired mrs register settings. jtag testing may then begin as soon as t mrsc is satisfied. jtag testing can be conducted after full initilization as well. the input signals of the test access port (tdi , tms, and tck) are referenced to the v dd as a supply, while the output driver of the tap (tdo) is powered by v ddq . the jtag test access port incorporates a st and ardtap controller from which the inst ruction register, bound ary scan register, bypass register, and id code register can be selected. each of these functions of the tap controller are described below. disabling the jtag feature use of the jtag port is never required for ram operation. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconn ected or they can be connected to v dd directly or through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. all of the states in the tap controller state diagram are entere d through the serial input of the tms pin. a ?0? in the diagram represents a low on the tms pin during the rising edge of tck while a ?1? represents a high on tms.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 53/64 ? 2011, gsi technology test data-in (tdi) the tdi ball is used to serially input test instructions and da ta into the registers and can be connected to the input of any o f the registers. the register between tdi and tdo is chosen by the in struction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap cont roller state diagram. tdi is conn ected to the most significant bit (msb) of any register (see the tap controller block diagram). test data-out (tdo) the tdo output ball is used to serially clock test instructions and data out from the registers. the tdo output driver is only active during the shift-ir and shift-dr tap controller states. in all ot her states, the tdo pin is in a high-z state. the output chang es on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register (see the tap controller block diagram). tap controller the tap controller is a finite state machine that uses the state of the tms pin at the rising edge of tck to navigate through i ts various modes of operation. the tap controller state diagram can be seen in the tap controller state diagram. each state is described in detail below. test-logic-reset the test-logic-reset controller st ate is entered when tms is held high for at least five consecuti ve rising edges of tck. as lo ng as tms remains high, the tap controller will remain in the test-log ic-reset state. the test logic is inactive during this state. run-test/idle the run-test/idle is a cont roller state in between scan operat ions. this state can be maintained by holding tms low. from here either the data register scan, or subsequently, the instruction register scan can be selected. select-dr-scan select-dr-scan is a temporary controll er state. all test data registers re tain their previous state while here. capture-dr the capture-dr state is where the data is parallel-loaded into the test data register s. if the boundary scan register is the cu rrently selected register, then the data currently on the pins is latched into the test data registers. shift-dr data is shifted serially through the data re gister while in this state. as new data is input through the tdi pin, data is shift ed out of the tdo pin. exit1-dr, pause-dr, and exit2-dr the purpose of exit1-dr is used to provide a path to return back to the run-test/idle state (through the update-dr state). the pause-dr state is entered when the shifting of data through the te st registers needs to be suspended. when shifting is to recon vene, the controller enters the exit2-dr state an d then can re-enter the shift-dr state. update-dr when the extest instruction is selected, th ere are latched parallel outputs of the boun dary scan shift register that only chang e state during the update-dr controller state. instruction register states the instruction register states of the tap controller are similar to the data register states. the desired instruction is seria lly shifted into the instruction register during the shift-ir state and is loaded dur ing the update-ir state.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 54/64 ? 2011, gsi technology loading instruction code and shifting out data t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 logic-reset idle select-dr select-ir capture-ir shift-ir shift-ir exit 1-ir pause-ir pause-ir 8-bit instruction code 8-bit instruction code tck tms tdi tap state tdo loading instruction code and shifting out data (continued) t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 exit 2-ir update-ir select-dr capture-dr shift-dr shift-dr shift-dr exit 1-dr update-dr idle n-bit register between tdi and tdo n-bit register between tdi and tdo tck tms tdi tap state tdo
select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 1 preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 55/64 ? 2011, gsi technology jtag tap controller state diagram
x 1 . . . . . 2 1 0 31 30 29 . . . 2 1 0 0 7 6 5 4 3 2 1 0 selection circuitry selection circuitry tdo tdi bypass regsiter instruction regsiter identification regsiter boundary scan regsiter tck tms tap controller note: x= 112 for all configurations preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 56/64 ? 2011, gsi technology tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v ddq ) for five rising edges of tck. this re set does not affect the operation of the lldram ii and may be performed while the lldram ii is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be s canned into and out of the lldram ii test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register eight-bit instructions can be seri ally loaded into the instructi on register. this register is lo aded during the update-ir state of the tap controller. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcod e instruction if the controller is placed in a rese t state as described in the previous section. when the tap controller is in the capture-ir state, the two lsbs are load ed with a binary ?01? pattern to allow for fault isola tion of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is so metimes advantageous to skip certain chips. the bypass regi ster is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the lldram ii wi th minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 57/64 ? 2011, gsi technology boundary scan register the boundary scan register is connected to al l the input and bidirectional balls on the lldram ii. several balls are also inclu ded in the scan register to reserved balls. the lldram ii has a 113-bit register. the boundary scan register is loaded with the contents of the ra m i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the boundary scan register table shows the order in which the bi ts are connected. each bit corres ponds to one of the balls on t he lldram ii package. the msb of the register is co nnected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-d r state when the idcode command is loaded in the instruction register. the idcode is hardwired into the lldram ii and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the table below. identification register definitions instruction field bit size bit size revision number (31:28) abcd ab = die revision cd = 00 for x9, 01 for x18 device id (27:12) 00jkidef10100111 def = 000 for 288mb, 001 for 576mb i = 0 for common i/o, 1 for separate i/o jk = 01 for lldram ii gsi jedec id code (11:1) 00011011001 allows unique identification of lldram ii vendor id register presence indicator (0) 1 indicates the presence of an id register tap instruction set overview many different instructions (2 8 ) are possible with the 8-bit instruction register. all combinations used are listed in the instruction codes table. these six instructions are described in detail belo w. the remaining instructions are reserved and should not be us ed. the tap controller used in this lldram ii i s fully compliant to the 1149.1 convention. instructions are loaded into th e tap controller during the shift-ir state when the instruction regi ster is placed between tdi a nd tdo. during this state, instructions are shifted through the inst ruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controll er needs to be moved in to the update-ir state. extest the extest instruction allows circuitry external to the component package to be tested. boundary scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls. idcode the idcode instruction causes a vendor-s pecific, 32-bit code to be loaded into the instructi on register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 58/64 ? 2011, gsi technology high-z the high-z instruction causes the boundary scan register to be connected between the tdi and tdo. this places all lldram ii outputs into a high-z state. clamp when the clamp instruction is loaded into the inst ruction register, the data driven by the output balls are determined from the values held in the boundary scan register. sample/preload when the sample/preload instruction is load ed into the instruction re gister and the tap controll er is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap contro ller clock can only operate at a frequency up to 50 mhz, while the lldram ii clock operates significantly faster. because there is a large difference between the clock fre quencies, it is possible that during th e capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this w ill not harm the device, but there is no guarantee as to the value th at will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the corre ct value of a signal, the lldram ii signal must be stabilized l ong enough to meet the tap controller?s capture setup plus hold time ( t cs + t ch). the lldram ii clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/pr eload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bou ndary scan register between the tdi and tdo balls. bypass when the bypass in s truction is loaded in the instructi on register and the tap is placed in a shift-dr state, the bypass registe r is placed between tdi and tdo. the ad vantage of the bypass instruction is that it shortens the bounda ry scan path when multiple devices are connected together on a board. reserved for future use the remaining instructions are not impl emented but are reserved for future use. do not use these instructions. tap timing t0 t1 t2 t3 t4 t5 ttlov ttlox tthdx tdvth tthmx tmvth tththtthth ttlthttlth tthtltthtl test clock (tck) test mode select (tms) test data-in (tdi) test data-out (tdo)
tap input ac logic levels description symbol min max units input high (logic 1) voltage v ih v ref + 0.3 ? v input low (logic 0) voltage v il ? v ref ? 0.3 v tap ac electrical characteristics description symbol min max units clock clock cycle time tthth 20 ? ns clock frequency ttf ? 50 mhz clock high time tthtl 10 ? ns clock low time ttlth 10 ? ns tdi/tdo times tck low to tdo unknown ttlox 0 ? ns tck low to tdo valid ttlov ? 10 ns tdi valid to tck high tdvth 5 ? ns tck high to tdi invalid tthdx 5 ? ns setup times tms setup tmvth 5 ? ns capture setup tcs 5 ? ns hold times tms setup tthmx 5 ? ns capture setup tch 5 ? ns note: tcs and tch refer to the set up and hold time requirements of latching data from the boundary scan register. preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 59/64 ? 2011, gsi technology
tap dc electrical characteri stics and operating conditions description condition symbol min max units notes input high (logic 1) voltage ? v ih v ref + 0.15 v dd + 0.3 v 1, 2 input high (logic 0) voltage ? v il v ssq ? 0.3 v ref ? 0.15 v 1, 2 input leakage current output disabled, 0 v v in v ddq i li ?5.0 5.0 ? ? output leakage current 0 v v in v dd i lo ?5.0 5.0 ? ? output low voltage i olc = 100 ? v ol 1 ? 0.2 v 1 output low voltage i olt = 2ma v ol 2 ? 0.4 v 1 output high voltage ? i ohc ? = 100 ? v oh 1 v ddq ? 0.2 ? v 1 output high voltage ? i oht ? = 2ma v oh 2 v ddq ? 0.4 ? v 1 notes: 1. all voltages referenced to v ss (gnd). 2. overshoot = v ih(ac) v dd + 0.7 v for t tthth/2; undershoot = v il(ac) ? 0.5 v for t tthth/2; during normal operation, v ddq must not exceed v dd. scan register sizes register name bit size instruction 8 bypass 1 id 32 boundary scan 113 jtag tap instruction codes instruction code description extest 0000 0000 captures i/o ring contents; places the boundary scan register betwen tdi and tdo; this operation does not affect lldram ii operations. idcode 0010 0001 loads the id register with the vendor id code and places the r egister between tdi and tdo; this operation does not affect lldram ii operations. sample/preload 0000 0101 captures i/o ring contents. places the boundary scan register between tdi an d tdo. clamp 0000 0111 selects the bypass register to be connected between tdi and tdo; data driven by output balls are determined from values held in the boundary scan register. high-z 0000 0011 selects the bypass register to be connected bet ween tdi and tdo; all outputs are forced into high-z. bypass 1111 1111 places bypass register between tdi and tdo. this operation does not af fect lldram ii operations. preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 60/64 ? 2011, gsi technology
boundary scan exit order bit # ball bit # ball bit # ball 1 k1 39 r11 77 c11 2 k2 40 r11 78 c11 3 l2 41 p11 79 c10 4 l1 42 p11 80 c10 5 m1 43 p10 81 b11 6 m3 44 p10 82 b11 7 m2 45 n11 83 b10 8 n1 46 n11 84 b10 9 p1 47 n10 85 b3 10 n3 48 n10 86 b3 11 n3 49 p12 87 b2 12 n2 50 n12 88 b2 13 n2 51 m11 89 c3 14 p3 52 m10 90 c3 15 p3 53 m12 91 c2 16 p2 54 l12 92 c2 17 p2 55 l11 93 d3 18 r2 56 k11 94 d3 19 r3 57 k12 95 d2 20 t2 58 j12 96 d2 21 t2 59 j11 97 e2 22 t3 60 h11 98 e2 23 t3 61 h12 99 e3 24 u2 62 g12 100 e3 25 u2 63 g10 101 f2 26 u3 64 g11 102 f2 27 u3 65 e12 103 f3 28 v2 66 f12 104 f3 29 u10 67 f10 105 e1 30 u10 68 f10 106 f1 31 u11 69 f11 107 g2 32 u11 70 f11 108 g3 33 t10 71 e10 109 g1 34 t10 72 e10 110 h1 35 t11 73 e11 111 h2 36 t11 74 e11 112 j2 37 r10 75 d11 113 j1 38 r10 76 d10 ? ? preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 61/64 ? 2011, gsi technology boundary scan (bsdl files) for information regarding the boundary scan chain, or to obta in bsdl files for this part, please contact our applications engineering department at: apps@gsitechnology.com .
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 62/64 ? 2011, gsi technology package dimensions?144-bump bga (package l) a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10 11 12 12 11 10 9 8 7 6 5 4 3 2 1 a1 a1 0.80 typ. 11.000.10 17.00 ctr ?0.51 (144x) a seating plane 1.20 max 0.012 a 10 typ. 10.60 ctr. a b c d e f g h j k l m n p r t u v 1.0 typ. 8.80 18.500.10 0.730.1 note: all dimensions in millimeters. 8.8 ctr 0.8 typ 0.34 min 18.1 ctr 0.490.05
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 63/64 ? 2011, gsi technology ordering information for gsi lldram? iis org part number 1 type package speed (tck/trc) t 2 64m x 9 gs4576s09l-18 sio lldram ii 144-ball bga 533/15 c 64m x 9 gs4576s09l-24 sio lldram ii 144-ball bga 400/15 c 64m x 9 gs4576s09l-25 sio lldram ii 144-ball bga 400/20 c 64m x 9 gs4576s09l-33 sio lldram ii 144-ball bga 300/20 c 32m x 18 gs4576s18l-18 sio lldram ii 144-ball bga 533/15 c 32m x 18 gs4576s18l-24 sio lldram ii 144-ball bga 400/15 c 32m x 18 gs4576s18l-25 sio lldram ii 144-ball bga 400/20 c 32m x 18 gs4576s18l-33 sio lldram ii 144-ball bga 300/20 c 64m x 9 gs4576s09gl-18 sio lldram ii rohs-compliant 144-ball bga 533/15 c 64m x 9 gs4576s09gl-24 sio lldram ii rohs-compliant 144-ball bga 400/15 c 64m x 9 gs4576s09gl-25 sio lldram ii rohs-compliant 144-ball bga 400/20 c 64m x 9 gs4576s09gl-33 sio lldram ii rohs-compliant 144-ball bga 300/20 c 32m x 18 gs4576s18gl-18 sio lldram ii rohs-compliant 144-ball bga 533/15 c 32m x 18 gs4576s18gl-24 sio lldram ii rohs-compliant 144-ball bga 400/15 c 32m x 18 gs4576s18gl-25 sio lldram ii rohs-compliant 144-ball bga 400/20 c 32m x 18 gs4576s18gl-33 sio lldram ii rohs-compliant 144-ball bga 300/20 c 64m x 9 gs4576s09l-18i sio lldram ii 144-ball bga 533/15 i 64m x 9 gs4576s09l-24i sio lldram ii 144-ball bga 400/15 i 64m x 9 gs4576s09l-25i sio lldram ii 144-ball bga 400/20 i 64m x 9 gs4576s09l-33i sio lldram ii 144-ball bga 300/20 i 32m x 18 gs4576s18l-18i sio lldram ii 144-ball bga 533/15 i 32m x 18 gs4576s18l-24i sio lldram ii 144-ball bga 400/15 i 32m x 18 gs4576s18l-25i sio lldram ii 144-ball bga 400/20 i 32m x 18 gs4576s18l-33i sio lldram ii 144-ball bga 300/20 i 64m x 9 gs4576s09gl-18i sio lldram ii rohs-compliant 144-ball bga 533/15 i 64m x 9 gs4576s09gl-24i sio lldram ii rohs-compliant 144-ball bga 400/15 i 64m x 9 gs4576s09gl-25i sio lldram ii rohs-compliant 144-ball bga 400/20 i note: 1. customers requiring delivery in tape and r eel should add the character ?t? to the end of the part number. example: gs4576s09- 533t. 2. c = commercial temperature range. i = industrial temperature range.
preliminary gs4576s09/18l specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.01 4/2011 64/64 ? 2011, gsi technology 64m x 9 gs4576s09gl-33i sio lldram ii rohs-compliant 144-ball bga 300/20 i 32m x 18 gs4576s18gl-18i sio lldram ii rohs-compliant 144-ball bga 533/15 i 32m x 18 gs4576s18gl-24 sio lldram ii rohs-compliant 144-ball bga 400/15 i 32m x 18 gs4576s18gl-25i sio lldram ii rohs-compliant 144-ball bga 400/20 i 32m x 18 gs4576s18gl-33i sio lldram ii rohs-compliant 144-ball bga 300/20 i 576mb lldram ii datasheet revision history ds/daterev. code: old; new types of changes format or content page;revisions;reason 4576sxx_r1 ? creation of new datasheet ordering information for gsi lldram? iis (continued) org part number 1 type package speed (tck/trc) t 2 note: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. example: gs4576s09- 533t. 2. c = commercial temperature range. i = industrial temperature range.

▲Up To Search▲

Price & Availability of GS4576S18GL-24IT

	To Download GS4576S18GL-24IT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .